1. Field of the Invention
This invention is related to a high-gain converter, and more particularly relates to semiconductor circuitry which is provided on gallium arsenide (Ga As) integrated circuitry for converting Emitter Coupled Logic (ECL) input signals to be employed directly in Ga As logic. Thus, ECL output voltage levels may be directly read by Ga As integrated circuits.
2. Description of the Prior Art
Numerous different types or families of integrated circuits are commercially available. Manufacturers of integrated circuits usually produce families of devices which are completely compatible with each other. Many families of integrated circuits have characteristics which are similar and permit designers to mix families in the same system to obtain optimum performance.
It is not uncommon for families of integrated circuits to be incompatible and when the characteristics of such incompatible families of devices are not matched, some form of signal conversion is required to assure that logic signals are properly sensed and/or processed.
More than one type of problem can arise when two different types of logic are being connected in a system. The power supply levels may be different and the logic voltage swings may be different. The signals may also require reshaping, amplification and/or attenuation.
When the conversion or translation is from slower speed logic to faster speed logic, it is also important that the conversion logic does not create an inordinate time delay, otherwise, the reason for using a high-speed logic can be defeated by time delays at the interface converter.
These problems are understood and have been considered in typical translators and converters sold by numerous semiconductor houses including Motorola Inc. for interfacing ECL with transistor-transistor logic (TTL). These commercially available translators and converters can not be used or modified for use with ECL and Ga As logic without encountering some of the aforementioned problems as well as the problems of stability, switching time and ringing which occur with high-speed logic circuits.
It would be desirable to avoid or eliminate the known and understood problems of translation and/or conversion when adapting a conversion circuit for ECL to Ga As. Further, it would be highly desirable to provide the conversion circuitry as part of the input circuitry of the high-speed logic and to provide this logic as part of the integrated circuit being driven without the requirement of additional discrete components which would slow down the converter.
It would also be desirable if the converter or translating circuit has as few stages of logic as possible and that they be free of generated noise and also be compensated against age degradation and temperature variations. Further, it would be desirable that the translating or compensating network be free from variations due to power supply voltages.